1. Field of the Invention
This invention relates to semiconductor memories and, more particularly, to means and methods for providing integrated bipolar SCR devices and circuits for memory arrays.
2. Background Art
It is commonplace in the semiconductor art to form SCR like devices using coupled complementary bipolar transistors. These SCR's are cross-coupled to form a bi-stable storage cell. Large numbers of such storage cells are placed in an addressable array to form a memory. Tens of thousands of such cells are often used in a single memory array.
The SCR is composed a PNP and a NPN device wherein the collector of one transistor is formed in the same region as the base of the other transistor. In the bipolar integrated circuit art, the NPN device is usually formed as a vertical transistor and the PNP is usually formed as a lateral transistor. This arrangement gives switching action even though the gain of the lateral PNP is not large since it is only necessary that the product of the common emitter current gains of the device pair be equal to or greater than one.
While the lateral-vertical device arrangement is useful for memory cells, it suffers from a number of disadvantages. Among these are the fact that the lateral device, e.g., the PNP, injects a small amount of current into the substrate. A parasitic PNN.sup.+ P transistor exists between the P injector or emitter of the lateral PNP and the underlying P substrate on which all of the devices are built. While the presence of the intervening N.sup.+ region reduces the gain of this parasitic device to a small value, there is still a finite amount of conduction to the substrate through this parasitic device. Where only a few lateral PNP devices are used, this leakage current is not troublesome. However, in large memory arrays employing thousands or tens of thousands of devices, the sum of the small parasitic leakage currents of the many lateral PNP devices can account for a substantial fraction of the quiescent power loss in the memory array. A further limitation of prior art lateral devices is their high charge storage. Charge storage undesirably increases switching time so that memory speed is less than what is desired. Thus a need still exists for improved device structures which reduce or substantially eliminate excess charge storage and leakage current.
One way to reduce the parasitic action is to replace the lateral device with a vertical device. However, prior art arrangements for accomplishing this in integrated circuits have all required the use of isolating structures between the vertical PNP and vertical NPN, such as trenches, oxide filled moats, or additional diffused regions. These isolation structures increase the semiconductor area required for implementing the memory cell. Since many thousands of memory cells may be required in a single semiconductor die, device structures which occupy increased area are not desirable. Further, it is important that the device structure be easy to fabricate and not require the addition of many more process steps, as is the case with prior art trench structures or dielectric isolation structures. Thus a need continues to exist for improved memory cell structures which do not require additional isolation walls and large increases in device area, and which can be fabricated using inexpensive and convenient process steps.
Accordingly, it is an object of the present invention to provide improved latching devices and memory cell structures which do not depend on lateral devices.
It is a further object of the present invention to provide improved latching devices with reduced charge storage and substrate leakage current.
It is an additional object of the present invention to provide improved SCR latching devices formed from vertical PNP and NPN devices in the same monolithic substrate.
It is a further object of the present invention to provide an improved SCR latching device without isolation walls between the coupled PNP and NPN devices forming the latching device.
It is an additional object of the present invention to provide improved latching devices which can be conveniently arranged in pairs to provide bi-stable memory cells.
It is a further object of the present invention to provide the above latching devices and bi-stable memory cells in a minimum area.
It is an additional object of the present invention to provide an improved method for fabrication of the above device and cell structures.
For convenience, the present invention is illustrated for the case of devices and circuits built on P type substrates. Those of skill in the art will understand that N type substrates could equally well be used, in which case the illustrated device regions would have conductivity types opposite those shown.
SUMMARY OF THE INVENTION
These and other objects and advantages are provided by the present invention wherein, a vertical PNP and vertical NPN are used for the coupled transistor pair forming the SCR. A P.sup.+ collector is provided for the vertical PNP which is internally tied to the base of the vertical NPN. An N.sup.+ subcollector is provided for the NPN. A common N region is used to form the base of the PNP and the collector of the NPN. Unlike many prior art structures for forming complementary vertical devices, the invented structure uses no isolation walls or metallic interconnections between the PNP and NPN devices making up the SCR. Each SCR is contained within a single isolation tub. Pairs of these integrated SCRs are interconnected to make up a memory cell.
When a P type substrate is used, for example, it has thereon an N.sup.+ buried collector, covered in turn with an N type epi-regio which serves as the collector of a vertical NPN device and the base of a vertical PNP device. The collector of the vertical PNP device is formed from a buried P.sup.+ region which underlies the N epi-region and overlies the N.sup.+ buried collector. A P type base for the vertical NPN is placed in the N epiregion over the N.sup.+ buried collector. A portion of the P-base overlaps the P.sup.+ buried collector for the vertical PNP. The P type emitter or injector of the vertical PNP is formed in the N epi-region over the P.sup.+ buried collector. This P type injector or emitter region for the vertical PNP is preferably formed at the same time as the P type base of the vertical NPN. In order for the PNP and NPN to be coupled to form an SCR, the P.sup.+ collector of the PNP must be tied to the P type base of the NPN and the N type base of the PNP must be tied to the N type collector of the NPN. This is accomplished in the present invention by placing the two devices side by side in a common N type region surrounded by an isolation moat extending to the substrate and with an overlap region between the NPN base and the PNP collector. An internal P type plug of limited lateral area is provided through the N epi-region from the P base to the P.sup.+ buried collector in the overlap region. This couples the P base and P.sup.+ collector together. It is essential that the P-plug not extend across the device from isolation wall to isolation wall since the N base region of the PNP must remain coupled to the N collector region of the NPN around or between the P type plug. The P plug is conveniently formed by ion implantation at sufficient energy to insure that it is formed beneath the device surface in the N region where the P base and P.sup.+ collector overlap. The invented means permits the PNP and NPN devices to be formed in a single isolation tub. Multiple tubs may be conveniently arranged in a side-by-side fashion to permit economical constriction of cross-coupled devices for memory cells.